How to drive a 3.81 inch 1080x1200 AMOLED with FPGA?

How to Drive a 3.81 Inch 1080x1200 AMOLED with FPGA

To drive a 3.81 inch 1080x1200 amoled display with an FPGA, you need to handle the MIPI DSI interface, generate the required pixel clock, and manage the display’s power sequencing. The panel typically uses a 4-lane MIPI DSI with a pixel clock around 300 MHz to achieve 60 Hz refresh rate. For a 1080x1200 resolution, the total active pixels are 1,296,000, and with blanking overhead, the total per frame is about 1,440,000 pixels. At 60 Hz, that’s 86.4 million pixels per second, requiring a 4-lane MIPI DSI link running at roughly 864 Mbps per lane, or a total of 3.456 Gbps. You’ll need an FPGA with integrated MIPI D-PHY hard macros, like the Xilinx Artix-7 or Lattice ECP5, to handle the high-speed serial data. The display’s internal driver IC, often an RM69090 or similar, expects a specific initialization sequence via MIPI commands, including setting the sleep-out, display-on, and gamma correction. Power supply rails are critical: you need 1.8V for the I/O, 3.3V for the analog, and a boost converter for the ELVSS (typically -2.5V to -4.5V). The FPGA must also generate a backlight PWM signal, though AMOLEDs don’t use a backlight—they self-emit, so you control brightness via the ELVSS voltage or a dimming command. Timing-wise, you must meet the VESA standard for horizontal and vertical blanking: for 1080x1200, typical HFP is 40, HSYNC is 4, HBP is 20, VFP is 4, VSYNC is 2, VBP is 4, giving a total pixel clock of 1080+40+4+20 = 1144 per line, and 1200+4+2+4 = 1210 lines, resulting in a 1,384,240 total pixels per frame. At 60 Hz, that’s 83.05 MHz pixel clock, but MIPI DSI uses a serialized stream, so the actual lane speed is pixel clock multiplied by number of bits per pixel (24-bit RGB) divided by number of lanes. For 4 lanes, that’s 83.05 MHz * 24 / 4 = 498.3 Mbps per lane, which is well within the D-PHY spec. However, the display’s datasheet might specify a higher clock for overdrive or variable refresh rate, so check the exact timing requirements. The FPGA’s logic must include a MIPI DSI transmitter core, which handles packetization, CRC, and ECC. You can use open-source IP like the MIPI DSI from the Lattice Radiant software or a custom VHDL/Verilog implementation. The initialization sequence involves sending DCS commands like 0x11 (Sleep Out), 0x29 (Display On), and 0x3A (Set Pixel Format) for 24-bit RGB. The power-up sequence is strict: first apply VDDI (1.8V), then VDD (3.3V), then the ELVSS, and finally the MIPI clock. The FPGA must wait at least 10 ms after power-up before sending commands. The display’s typical power consumption is around 500 mW at 60 Hz, with peak current of 150 mA on the 3.3V rail. You’ll need a voltage regulator with low dropout, like the TPS63020, to handle the 1.5A peak during high-brightness scenes. The FPGA’s I/O pins must be configured for LVDS or sub-LVDS levels to match the MIPI D-PHY, which uses 200 mV differential swing. Most FPGAs require external termination resistors (100 ohms differential) on each lane. The clock lane runs at half the data rate in some modes, but for this display, it’s typically 1/4 of the data rate. The MIPI interface also requires a low-power mode for command transmission, which uses a 10 MHz clock. The FPGA must handle the transition between high-speed and low-power modes. The display’s resolution is non-standard at 1080x1200, which is a square-ish aspect ratio (0.9:1), so you might need to scale the input if using a standard video source. The FPGA can implement a line buffer to store the input and then output at the correct timing. The total memory required is 1080 * 24 bits = 25,920 bits per line, but you’ll need double buffering, so 51,840 bits, which fits in most FPGA block RAMs. The pixel clock for the input can be derived from a PLL, but the output must be synchronized to the MIPI clock. The display’s datasheet often specifies a maximum pixel clock of 100 MHz, so you have headroom. The ELVSS voltage directly affects brightness: at -2.5V, the display is dimmest, and at -4.5V, it’s brightest. You can control this via a DAC or a PWM-driven boost converter. The FPGA can generate a PWM signal with a 10 kHz frequency and 8-bit resolution to set the ELVSS target. The display also has a TE (tearing effect) output pin, which indicates the start of a new frame. The FPGA can use this as a sync signal to avoid tearing. The TE pin is an open-drain output, so you need a pull-up resistor to 1.8V. The timing diagram shows that TE pulses low for 1 line period at the start of the vertical blanking. The FPGA must wait for this pulse before sending new frame data. The display’s internal SRAM is 1080x1200x24 bits, which is about 3.7 MB, but it’s not accessible externally—you only write to it via MIPI. The MIPI DSI protocol uses packets: short packets for commands and long packets for pixel data. Each long packet has a 4-byte header, a 2-byte checksum, and a variable-length data payload. The FPGA must compute the CRC for each packet. The CRC polynomial is 0x1021 (CRC-16-CCITT). The data payload is aligned to 4 bytes, so you might need padding. For 24-bit RGB, each pixel is 3 bytes, but the MIPI interface expects 4-byte alignment, so you can pack 4 pixels into 12 bytes or use a 32-bit bus. The display’s driver IC might support 18-bit or 16-bit modes, but 24-bit gives the best color depth. The gamma correction is stored in the IC’s registers, and you can adjust it via MIPI commands. The default gamma curve is typically linear, but you can load custom values for better color accuracy. The FPGA can store gamma tables in ROM and send them during initialization. The display’s viewing angle is 178 degrees, typical for AMOLED, but the color shift at extreme angles is minimal. The contrast ratio is 100,000:1, which is standard for AMOLED. The response time is 0.1 ms, so motion blur is negligible. The display’s lifetime is rated at 30,000 hours at 50% brightness, but the blue subpixels degrade faster. To mitigate this, you can implement a pixel shifting algorithm in the FPGA to spread the wear. The display’s pixel arrangement is RGB stripe, but some AMOLED panels use PenTile, so check the datasheet. The 3.81 inch panel likely uses a standard RGB stripe. The physical dimensions are 3.81 inches diagonal, which is about 96.8 mm, with an active area of 82.4 mm x 91.6 mm (assuming 0.0763 mm pixel pitch). The MIPI connector is a 30-pin FPC with 0.5 mm pitch, so you need a matching connector on the FPGA board. The pinout includes VDDI, VDD, ELVSS, GND, MIPI lanes (D0+, D0-, D1+, D1-, D2+, D2-, D3+, D3-), CLK+, CLK-, TE, and RESET. The RESET pin is active low, and you must hold it low for at least 10 ms after power-up. The FPGA can generate a reset signal using a GPIO. The display’s operating temperature range is -20°C to 70°C, so it’s suitable for consumer electronics. The FPGA must be able to handle the thermal load: the Artix-7 consumes about 100 mW per 100 MHz of logic, so a 50 MHz design uses 50 mW, plus the MIPI PHY power of 20 mW per lane. The total FPGA power is around 150 mW, which is manageable. The PCB layout for the MIPI traces must have controlled impedance of 100 ohms differential, with trace lengths matched to within 5 mm. The FPGA’s differential outputs should be routed to the connector with no vias if possible. The clock lane should be shielded by ground traces. The ELVSS supply requires a low-noise boost converter, like the TPS61040, which can generate up to -5V from a 3.3V input. The output ripple should be less than 10 mV to avoid flicker. The FPGA can monitor the ELVSS voltage via an ADC to ensure stability. The display’s typical brightness is 350 cd/m², but you can achieve 600 cd/m² with higher ELVSS. The power consumption scales linearly with brightness: at 350 cd/m², the display draws 300 mA at 3.3V, which is 1W. The FPGA must have a heatsink if the ambient temperature exceeds 50°C. The MIPI DSI interface also supports command mode, where you can write to a frame buffer in the display’s RAM. This is useful for low-power static images. The FPGA can send a single frame and then switch to low-power mode, reducing power to 10 mW. The display’s refresh rate can be reduced to 1 Hz for static content, but the ELVSS must be maintained to avoid flicker. The FPGA can implement a frame counter to trigger updates. The display’s driver IC might have a built-in self-refresh mode, which you can enable via a command. The FPGA can then go into sleep mode, waking up only for updates. The MIPI interface has a low-power state where the clock lane is stopped, and the data lanes are in high-impedance. The FPGA must detect when the display is ready by polling the TE pin. The display’s initialization sequence is critical: after power-up, send 0x01 (Software Reset), wait 5 ms, then 0x11 (Sleep Out), wait 120 ms, then 0x29 (Display On), wait 20 ms. The gamma settings are sent after Sleep Out. The typical gamma values are 0x02, 0x03, 0x04, etc., but they vary by manufacturer. The FPGA can store the full sequence in a ROM and send it via a state machine. The MIPI DSI protocol uses a 16-bit command number, but DCS commands use 8-bit. The FPGA must handle the packet type: 0x15 for short packet write, 0x05 for short packet read, and 0x39 for long packet write. The pixel data is sent using 0x39 with a data type of 0x2C (write memory). The display’s memory is organized as a 1080x1200 matrix, and you can write to it row by row. The FPGA can use a DMA-like engine to fetch pixel data from external memory, like DDR3, if you have a large frame buffer. The FPGA’s block RAM can hold only a few lines, so for full-frame video, you need external memory. The MIPI interface’s bandwidth is sufficient for 60 fps, but if you use 120 fps, the pixel clock doubles to 166 MHz, and the lane speed goes to 996 Mbps per lane, which is near the limit of D-PHY. The display might support 120 Hz, but the datasheet must confirm. The FPGA’s PLL must be able to generate the required clock frequencies. The Artix-7 has PLLs that can output up to 800 MHz, so it’s fine. The MIPI D-PHY requires a reference clock of 26 MHz or 19.2 MHz, which you can generate from an external oscillator. The FPGA must also handle the D-PHY’s escape mode, which is used for low-power commands. The escape mode uses a 10 MHz clock and a special sequence. The FPGA’s MIPI hard macro usually handles this automatically. The display’s datasheet will specify the exact timing for the escape mode. The power consumption of the MIPI interface is about 10 mW per lane in high-speed mode. The total interface power is 50 mW for 4 lanes plus clock. The FPGA’s logic power is separate. The display’s ELVSS current depends on the brightness: at 50% brightness, it draws 50 mA, at 100% brightness, 150 mA. The boost converter efficiency is about 90%, so the input power is 1.1W at full brightness. The total system power is around 2W, which is typical for a small AMOLED. The FPGA can implement a brightness sensor to adjust the ELVSS automatically. The display’s color gamut is 100% DCI-P3, which is wider than sRGB. The FPGA can apply a color correction matrix to map the input to the display’s gamut. The matrix is 3x3 and can be implemented in hardware using multipliers. The gamma correction is separate. The display’s white point is 6500K, but you can adjust it via the RGB gain registers. The FPGA can store calibration data in EEPROM. The display’s lifetime is affected by the blue subpixel, so you can reduce the blue gain to extend lifespan. The FPGA can implement a histogram-based algorithm to adjust the brightness dynamically. The MIPI interface’s maximum cable length is about 15 cm at 500 Mbps, so keep the FPGA close to the display. The connector’s FPC cable should be shielded. The display’s ground plane must be connected to the FPGA’s ground with low impedance. The ELVSS supply must be filtered with a 10 uF capacitor. The FPGA’s I/O power must be from a separate regulator to avoid noise. The MIPI D-PHY requires a 1.2V supply for the PHY, which the FPGA’s internal regulator can provide. The display’s RESET pin must be pulled up to 1.8V with a 10k resistor. The TE pin is open-drain, so use a 4.7k pull-up. The FPGA’s GPIOs must be 1.8V tolerant. The display’s operating voltage is 1.8V for the I/O, so the FPGA’s bank must be set to 1.8V. The MIPI lanes are differential, so the FPGA’s differential pairs must be used. The placement of the FPGA should be close to the connector to minimize trace length. The PCB stackup should have a ground plane under the MIPI traces. The impedance control is critical: 100 ohms differential with a tolerance of 10%. The trace width for 0.5 mm pitch is typically 0.1 mm with 0.1 mm spacing. The dielectric constant of the PCB material affects the impedance. The FPGA’s MIPI hard macro often includes a PLL for clock recovery. The clock lane must be matched to the data lanes within 0.2 mm. The skew between lanes can cause data errors. The FPGA’s internal logic must handle the de-skewing. The display’s driver IC might have a built-in de-skew circuit, but it’s better to minimize it on the PCB. The MIPI specification requires a maximum skew of 0.15 UI, which is 150 ps at 1 Gbps. The FPGA’s I/O delays can be adjusted using the IODELAY primitives. The Artix-7 has IDELAY with 78 ps resolution. The FPGA can calibrate the delay at startup. The display’s initialization sequence must include a calibration command for the D-PHY. The typical command is 0x04 (Read DSI Error) to check the link. The FPGA can poll this register to ensure the link is stable. The display’s power-up sequence must be controlled by the FPGA’s state machine. The sequence is: apply VDDI (1.8V), wait 10 ms, apply VDD (3.3V), wait 10 ms, apply ELVSS, wait 10 ms, then de-assert RESET, wait 10 ms, then send MIPI commands. The power-down sequence is reverse: first send Sleep In, wait 120 ms, then assert RESET, then remove ELVSS, then VDD, then VDDI. The FPGA must implement this sequence to avoid damaging the display. The display’s datasheet might specify a minimum time between power rails. The ELVSS must be applied after VDD to avoid latch-up. The FPGA can use a power-good signal from the regulators to sequence the power. The display’s typical startup time is 200 ms. The FPGA can display a splash screen during this time. The MIPI interface’s low-power mode is used for the initial commands. The high-speed mode is used for pixel data. The FPGA must switch between modes correctly. The MIPI DSI specification defines a turnaround procedure for bus turnaround. The FPGA’s hard macro handles this. The display’s read commands are used for diagnostics. The FPGA can read the display’s ID register to verify the panel. The typical ID is 0x90 for the RM69090. The FPGA can also read the gamma registers to confirm the settings. The display’s temperature sensor is sometimes integrated, but not in this panel. The FPGA can use an external sensor to adjust the ELVSS for temperature compensation. The AMOLED’s efficiency drops at low temperatures, so you might need to increase the ELVSS. The FPGA can implement a lookup table for temperature compensation. The display’s brightness uniformity is typically 5%, but the FPGA can apply a spatial correction to improve it. The correction is a 2D lookup table stored in the FPGA’s memory. The MIPI interface’s bandwidth is sufficient for the